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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_ethif_mac_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__ethif.html">EMAC         (Ethernet MAC)</a> &raquo; <a class="el" href="group__group__ethif__data__structures.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Ethernet MAC detailed configurations. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a638e0ac00c462a4260b07768b49a7631"><td class="memItemLeft" align="right" valign="top"><a id="a638e0ac00c462a4260b07768b49a7631"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a638e0ac00c462a4260b07768b49a7631">bintrEnable</a></td></tr>
<tr class="memdesc:a638e0ac00c462a4260b07768b49a7631"><td class="mdescLeft">&#160;</td><td class="mdescRight">interrupts/events to enable on start <br /></td></tr>
<tr class="separator:a638e0ac00c462a4260b07768b49a7631"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3edcd93a3928cd02d9226e2534df0470"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__ethif__enums.html#gad9764b4814aafde4d609f3fa0ded4f58">cy_en_ethif_dma_data_buffer_len_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a3edcd93a3928cd02d9226e2534df0470">dmaDataBurstLen</a></td></tr>
<tr class="memdesc:a3edcd93a3928cd02d9226e2534df0470"><td class="mdescLeft">&#160;</td><td class="mdescRight">fixed burst length for DMA data transfers  <a href="#a3edcd93a3928cd02d9226e2534df0470">More...</a><br /></td></tr>
<tr class="separator:a3edcd93a3928cd02d9226e2534df0470"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adaa7d04a61f72a3f200181eee1a78e09"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#adaa7d04a61f72a3f200181eee1a78e09">u8dmaCfgFlags</a></td></tr>
<tr class="memdesc:adaa7d04a61f72a3f200181eee1a78e09"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA config register bits 24, 25 &amp; 26.  <a href="#adaa7d04a61f72a3f200181eee1a78e09">More...</a><br /></td></tr>
<tr class="separator:adaa7d04a61f72a3f200181eee1a78e09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25b860d095d4966661b850e0d77210ed"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__ethif__enums.html#gaf2092324e59845ec4d7e5e2ee03ca134">cy_en_ethif_dma_mdc_clk_div_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a25b860d095d4966661b850e0d77210ed">mdcPclkDiv</a></td></tr>
<tr class="memdesc:a25b860d095d4966661b850e0d77210ed"><td class="mdescLeft">&#160;</td><td class="mdescRight">divisor to generate MDC from pclk  <a href="#a25b860d095d4966661b850e0d77210ed">More...</a><br /></td></tr>
<tr class="separator:a25b860d095d4966661b850e0d77210ed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c343a9ff82561ad4b915eb70031d445"><td class="memItemLeft" align="right" valign="top"><a id="a0c343a9ff82561ad4b915eb70031d445"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a0c343a9ff82561ad4b915eb70031d445">u8rxLenErrDisc</a></td></tr>
<tr class="memdesc:a0c343a9ff82561ad4b915eb70031d445"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable discard of frames with length field error <br /></td></tr>
<tr class="separator:a0c343a9ff82561ad4b915eb70031d445"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0f6001cd74d9cc8778b7b72a6f5ff6f"><td class="memItemLeft" align="right" valign="top"><a id="ab0f6001cd74d9cc8778b7b72a6f5ff6f"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#ab0f6001cd74d9cc8778b7b72a6f5ff6f">u8disCopyPause</a></td></tr>
<tr class="memdesc:ab0f6001cd74d9cc8778b7b72a6f5ff6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">disable copying Rx pause frames to memory <br /></td></tr>
<tr class="separator:ab0f6001cd74d9cc8778b7b72a6f5ff6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a528d9c87aeba3d10e39a179337929a36"><td class="memItemLeft" align="right" valign="top"><a id="a528d9c87aeba3d10e39a179337929a36"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a528d9c87aeba3d10e39a179337929a36">u8chkSumOffEn</a></td></tr>
<tr class="memdesc:a528d9c87aeba3d10e39a179337929a36"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable checksum offload operation <br /></td></tr>
<tr class="separator:a528d9c87aeba3d10e39a179337929a36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab16be6f2d24b6308b1c7aee7f9d7734a"><td class="memItemLeft" align="right" valign="top"><a id="ab16be6f2d24b6308b1c7aee7f9d7734a"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#ab16be6f2d24b6308b1c7aee7f9d7734a">u8rx1536ByteEn</a></td></tr>
<tr class="memdesc:ab16be6f2d24b6308b1c7aee7f9d7734a"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable Rx of frames up to 1536 bytes <br /></td></tr>
<tr class="separator:ab16be6f2d24b6308b1c7aee7f9d7734a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abdd9fdf7c727c3b2f0ac480421604ad7"><td class="memItemLeft" align="right" valign="top"><a id="abdd9fdf7c727c3b2f0ac480421604ad7"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#abdd9fdf7c727c3b2f0ac480421604ad7">u8rxJumboFrEn</a></td></tr>
<tr class="memdesc:abdd9fdf7c727c3b2f0ac480421604ad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable Rx of jumbo frames <br /></td></tr>
<tr class="separator:abdd9fdf7c727c3b2f0ac480421604ad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34317d6ac27bc6c7d0ca2730eb924289"><td class="memItemLeft" align="right" valign="top"><a id="a34317d6ac27bc6c7d0ca2730eb924289"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a34317d6ac27bc6c7d0ca2730eb924289">u8enRxBadPreamble</a></td></tr>
<tr class="memdesc:a34317d6ac27bc6c7d0ca2730eb924289"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable Rx frames with non-standard preamble <br /></td></tr>
<tr class="separator:a34317d6ac27bc6c7d0ca2730eb924289"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e0fe83a65a60e96e4f2d9ecb8af329f"><td class="memItemLeft" align="right" valign="top"><a id="a3e0fe83a65a60e96e4f2d9ecb8af329f"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a3e0fe83a65a60e96e4f2d9ecb8af329f">u8ignoreIpgRxEr</a></td></tr>
<tr class="memdesc:a3e0fe83a65a60e96e4f2d9ecb8af329f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ignore IPG rx_er (NetCfg b30) <br /></td></tr>
<tr class="separator:a3e0fe83a65a60e96e4f2d9ecb8af329f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc7cf16591325717cc27d21b5534329f"><td class="memItemLeft" align="right" valign="top"><a id="adc7cf16591325717cc27d21b5534329f"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#adc7cf16591325717cc27d21b5534329f">u8storeUdpTcpOffset</a></td></tr>
<tr class="memdesc:adc7cf16591325717cc27d21b5534329f"><td class="mdescLeft">&#160;</td><td class="mdescRight">u8storeUdpTcpOffset <br /></td></tr>
<tr class="separator:adc7cf16591325717cc27d21b5534329f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af453a4d843d5482cb0358e6271215e0f"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#af453a4d843d5482cb0358e6271215e0f">u8aw2wMaxPipeline</a></td></tr>
<tr class="memdesc:af453a4d843d5482cb0358e6271215e0f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of outstanding AXI write requests, that can be issued by DMA via the AW channel.  <a href="#af453a4d843d5482cb0358e6271215e0f">More...</a><br /></td></tr>
<tr class="separator:af453a4d843d5482cb0358e6271215e0f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af7369dfd71fcc09238ea1693aa472795"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#af7369dfd71fcc09238ea1693aa472795">u8ar2rMaxPipeline</a></td></tr>
<tr class="memdesc:af7369dfd71fcc09238ea1693aa472795"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of outstanding AXI read requests, that can be issued by DMA via the AR channel.  <a href="#af7369dfd71fcc09238ea1693aa472795">More...</a><br /></td></tr>
<tr class="separator:af7369dfd71fcc09238ea1693aa472795"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d5cad156d1011eecf94cfd0d16ada9e"><td class="memItemLeft" align="right" valign="top"><a id="a9d5cad156d1011eecf94cfd0d16ada9e"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a9d5cad156d1011eecf94cfd0d16ada9e">u8pfcMultiQuantum</a></td></tr>
<tr class="memdesc:a9d5cad156d1011eecf94cfd0d16ada9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable pfc multiple quantum (8 different priorities) <br /></td></tr>
<tr class="separator:a9d5cad156d1011eecf94cfd0d16ada9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4dc190233f2228c8461ec0e775693cc2"><td class="memItemLeft" align="right" valign="top"><a id="a4dc190233f2228c8461ec0e775693cc2"></a>
<a class="el" href="structcy__stc__ethif__wrapper__config__t.html">cy_stc_ethif_wrapper_config_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a4dc190233f2228c8461ec0e775693cc2">pstcWrapperConfig</a></td></tr>
<tr class="memdesc:a4dc190233f2228c8461ec0e775693cc2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration for Wrapper. <br /></td></tr>
<tr class="separator:a4dc190233f2228c8461ec0e775693cc2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfd75433d23d888eb974afc2081c7a8e"><td class="memItemLeft" align="right" valign="top"><a id="adfd75433d23d888eb974afc2081c7a8e"></a>
<a class="el" href="structcy__stc__ethif__tsu__config__t.html">cy_stc_ethif_tsu_config_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#adfd75433d23d888eb974afc2081c7a8e">pstcTSUConfig</a></td></tr>
<tr class="memdesc:adfd75433d23d888eb974afc2081c7a8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configuration for TSU. <br /></td></tr>
<tr class="separator:adfd75433d23d888eb974afc2081c7a8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc72d1560698b98cd549dee0325545e7"><td class="memItemLeft" align="right" valign="top"><a id="abc72d1560698b98cd549dee0325545e7"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#abc72d1560698b98cd549dee0325545e7">btxq0enable</a></td></tr>
<tr class="memdesc:abc72d1560698b98cd549dee0325545e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Q0 Enable. <br /></td></tr>
<tr class="separator:abc72d1560698b98cd549dee0325545e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc2c9a47aaa0eed0912791e650ec4a82"><td class="memItemLeft" align="right" valign="top"><a id="abc2c9a47aaa0eed0912791e650ec4a82"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#abc2c9a47aaa0eed0912791e650ec4a82">btxq1enable</a></td></tr>
<tr class="memdesc:abc2c9a47aaa0eed0912791e650ec4a82"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Q1 Enable. <br /></td></tr>
<tr class="separator:abc2c9a47aaa0eed0912791e650ec4a82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77b1955b1d393f316d608446472a033c"><td class="memItemLeft" align="right" valign="top"><a id="a77b1955b1d393f316d608446472a033c"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a77b1955b1d393f316d608446472a033c">btxq2enable</a></td></tr>
<tr class="memdesc:a77b1955b1d393f316d608446472a033c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tx Q2 Enable. <br /></td></tr>
<tr class="separator:a77b1955b1d393f316d608446472a033c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad572b189a252d8eda08e302c437eca69"><td class="memItemLeft" align="right" valign="top"><a id="ad572b189a252d8eda08e302c437eca69"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#ad572b189a252d8eda08e302c437eca69">brxq0enable</a></td></tr>
<tr class="memdesc:ad572b189a252d8eda08e302c437eca69"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Q0 Enable. <br /></td></tr>
<tr class="separator:ad572b189a252d8eda08e302c437eca69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3589274834f6989f91303380121b779a"><td class="memItemLeft" align="right" valign="top"><a id="a3589274834f6989f91303380121b779a"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a3589274834f6989f91303380121b779a">brxq1enable</a></td></tr>
<tr class="memdesc:a3589274834f6989f91303380121b779a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Q1 Enable. <br /></td></tr>
<tr class="separator:a3589274834f6989f91303380121b779a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a30413251b899509aba4addd5c3260112"><td class="memItemLeft" align="right" valign="top"><a id="a30413251b899509aba4addd5c3260112"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a30413251b899509aba4addd5c3260112">brxq2enable</a></td></tr>
<tr class="memdesc:a30413251b899509aba4addd5c3260112"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Q2 Enable. <br /></td></tr>
<tr class="separator:a30413251b899509aba4addd5c3260112"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9dad12f393ec758b69561da3734c98c5"><td class="memItemLeft" align="right" valign="top"><a id="a9dad12f393ec758b69561da3734c98c5"></a>
<a class="el" href="group__group__ethif__data__structures.html#ga5fd803e52b06f17344a9f5eba0851adb">cy_ethif_buffpool_t</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__ethif__mac__config__t.html#a9dad12f393ec758b69561da3734c98c5">pRxQbuffPool</a> [CY_ETH_DEFINE_NUM_RXQS]</td></tr>
<tr class="memdesc:a9dad12f393ec758b69561da3734c98c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rx Queues buffer pool 32 bytes aligned. <br /></td></tr>
<tr class="separator:a9dad12f393ec758b69561da3734c98c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="a3edcd93a3928cd02d9226e2534df0470"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a3edcd93a3928cd02d9226e2534df0470">&#9670;&nbsp;</a></span>dmaDataBurstLen</h2>

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          <td class="memname"><a class="el" href="group__group__ethif__enums.html#gad9764b4814aafde4d609f3fa0ded4f58">cy_en_ethif_dma_data_buffer_len_t</a> cy_stc_ethif_mac_config_t::dmaDataBurstLen</td>
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<p>fixed burst length for DMA data transfers </p>
<p>bit4:0 amba_burst_length 1xxxx: attempt use burst up to 16 (CY_ETHIF_DMA_DBUR_LEN_16) 01xxx: attempt use burst up to 8 (CY_ETHIF_DMA_DBUR_LEN_8) 001xx: attempt use burst up to 4 (CY_ETHIF_DMA_DBUR_LEN_4) 0001x: always use single burst 00001: always use single burst (CY_ETHIF_AMBD_BURST_LEN_1) 00000: best AXI burst up to 256 beats </p>

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<h2 class="memtitle"><span class="permalink"><a href="#adaa7d04a61f72a3f200181eee1a78e09">&#9670;&nbsp;</a></span>u8dmaCfgFlags</h2>

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<p>DMA config register bits 24, 25 &amp; 26. </p>
<p>OR the following bit-flags to set corresponding bits - CY_ETHIF_CFG_DMA_DISC_RXP, CY_ETHIF_CFG_DMA_FRCE_RX_BRST, CY_ETHIF_CFG_DMA_FRCE_TX_BRST </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a25b860d095d4966661b850e0d77210ed">&#9670;&nbsp;</a></span>mdcPclkDiv</h2>

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          <td class="memname"><a class="el" href="group__group__ethif__enums.html#gaf2092324e59845ec4d7e5e2ee03ca134">cy_en_ethif_dma_mdc_clk_div_t</a> cy_stc_ethif_mac_config_t::mdcPclkDiv</td>
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<p>divisor to generate MDC from pclk </p>
<p>CY_ETHIF_MDC_DIV_BY_8 = 0 CY_ETHIF_MDC_DIV_BY_16 = 1 CY_ETHIF_MDC_DIV_BY_32 = 2 CY_ETHIF_MDC_DIV_BY_48 = 3 CY_ETHIF_MDC_DIV_BY_64 = 4 CY_ETHIF_MDC_DIV_BY_96 = 5 CY_ETHIF_MDC_DIV_BY_128 = 6 CY_ETHIF_MDC_DIV_BY_224 = 7 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af453a4d843d5482cb0358e6271215e0f">&#9670;&nbsp;</a></span>u8aw2wMaxPipeline</h2>

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<p>Maximum number of outstanding AXI write requests, that can be issued by DMA via the AW channel. </p>
<p>Must not be = 0 if using AXI as this would disable writes </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af7369dfd71fcc09238ea1693aa472795">&#9670;&nbsp;</a></span>u8ar2rMaxPipeline</h2>

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<p>Maximum number of outstanding AXI read requests, that can be issued by DMA via the AR channel. </p>
<p>Must not be = 0 if using AXI as this would disable reads </p>

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